Programmable logic devices (PLDs) are a well-known type of programmable IC that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
A CLB typically includes one or more lookup tables (LUTs) that can be programmed to implement logic functions, as well as one or more flip-flops for storing LUT output signals. FIG. 1 illustrates one such CLB. CLB 100 of FIG. 1 includes four similar slices SLICE_0-SLICE_3. Each slice includes two lookup tables (LUTs) 101 and 102, a write control circuit 105, two multiplexers MUX1 and MUX2, and two output memory elements 103 and 104. The lookup tables, write control circuit, multiplexers, and output memory elements are all controlled by configuration memory cells MC1-MC7. Note that at least some of configuration memory cells MC1-MC7 represent more than one memory cell. Additional configuration memory cells and logic elements are omitted from FIG. 1, for clarity.
Each LUT 101, 102 can function in any of several modes. When in lookup table mode, each LUT has four data input signals IN1-IN4 that are supplied by the FPGA interconnect structure (not shown) via input multiplexers (not shown). (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.) When in RAM mode, input data is supplied by an input terminal RAM_DI_1, RAM_DI_2 to the DI terminal of the associated LUT. RAM write operations in both LUTs are controlled by write control circuit 105, which supplies one or more write control signals W to both LUTs based on RAM control signals provided by the interconnect structure.
Each LUT 101, 102 provides a LUT output signal to an associated multiplexer MUX1, MUX2, which selects between the LUT output signal and an associated register direct input signal Reg_DI_1, Reg_DI_2 from the interconnect structure. Thus, each LUT can be optionally bypassed. The output of each multiplexer MUX1, MUX2 is provided to the data input terminal D of an associated output memory element (103, 104 respectively). Memory elements 103 and 104 are clocked by a clock signal CK (e.g., provided by a global clock network) and controlled by various other register control signals (e.g., from the interconnect structure or provided by configuration memory cells of the FPGA). Each memory element 103, 104 provides a registered output signal Q1, Q2. The output of each LUT 101, 102 is also provided to an output terminal OUT1, OUT2 of the CLE. Thus, each output memory element can be optionally bypassed. The slice also includes output multiplexers (not shown) that select from among the various output signals of the slice and provide the selected signals to the FPGA interconnect structure. These output multiplexers are also controlled by configuration memory cells (not shown).
A LUT is commonly implemented as a series of multiplexers controlled by configuration memory cells, e.g., as shown in FIG. 2. The LUT circuit illustrated in FIG. 2 can be used, for example, to implement LUTs 101, 102 of FIG. 1. Input signals IN1-IN4 control transmission gates 201 to select one from a series of values stored in configuration memory cells M0-M15. As is well known, a transmission gate can include one N-channel transistor and one P-channel transistor coupled in parallel, with the N- and P-channel transistors being gated by complementary input signals. (The complementary input signals driving transmission gates 201 are not illustrated in FIG. 2, for clarity, but are indicated by the insertion of a bubble above or below two paired triangles. A bubble above the transmission gate indicates a gate that is “on” when the pictured input signal is low, and “off” when the input signal is high. A bubble below the transmission gate indicates a gate that is “on” when the pictured input signal is high, and “off” when the input signal is low.) In the illustrated embodiment, inverters 211-214 and 221 are also included, to buffer the signals as they pass from the memory cells M0-M15 to the output terminal OUT.
Programmable ICs benefit from the ability to implement a wide variety of designs. Therefore, the ratio of combinational logic to flip-flops in a design is not always one-to-one, as in the CLB of FIG. 1. For example, some designs may consume a larger number of flip-flops than LUTs. In such cases, it is not uncommon for some of the LUTs to go unused because of the lack of available flip-flops. It is desirable to provide methods and circuits that allow programmable elements in a programmable IC to accommodate such variations.